1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to an instruction set architecture (ISA) on a computer architecture. More particularly, the present invention relates to an instruction word compression apparatus and an instruction word compression method for a very long instruction word (VLIW) computer.
2. Description of Related Art
A very long instruction word (VLIW) computer includes a plurality of functional units which simultaneously executes instruction words, and is configured in a computer architecture capable of reducing a requirement for executing all instructions by distributing input instruction words to functional units.
A number of instruction words which can be executed simultaneously are determined by a number of the plurality of functional units, and a number of effective instruction words, which can be simultaneously executed at each execution time, may be less than an ideal maximum number due to dependency between input effective instruction words.
In this instance, a no operation (NOP) instruction word is allocated to a functional unit that is not being operated at each execution time, and thereby a number of instruction words required to be stored at each execution time is increased. Accordingly, a study regarding an instruction compression method has been made to reduce additional storage space. An end code that informs about an end of an effective instruction group and a parallel bit are used in the instruction compression method.
However, with respect to the end code, a complex instruction allocation logic is required, and a size of the end code is too great. The parallel bit may not be applicable to a method of allocating a functional unit for an instruction based on a location of the instruction within an instruction group. Also, an interconnect network is additionally required for the parallel bit. The interconnect network sends an instruction to be executed to the functional unit which supports the instruction to be executed. The implementation of the parallel bit is significantly complex.
Accordingly, with respect to the parallel processing VLIW computer, a more effective instruction word compression method is earnestly required.